L3: An FPGA-based multilayer maze routing accelerator

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Abstract
  • This paper describes a multi-layer maze routing accelerator which uses a two-dimensional array of processing elements (PEs) implemented in an FPGA. Routing for an L-layer NXN grid is performed by an array of NXN PEs that time-multiplex each layer over the array. This accelerates the classic Lee Algorithm from O(LXd(2)) in software to O(LXd). Each PE can be implemented in 32 look up tables in a Xilinx Virtex-II FPGA, which makes possible routing arrays that are large enough to support detailed routing for VLSI. Cycle measurements show a speedup of 50-75 X over a 2.54 GHz Pentium 4 for a 4-layer 8 X 8 array and 93 X for a 4-layer 16 X 16 array.
TitleL3: An FPGA-based multilayer maze routing accelerator
CreatorNestor, John A.
PublisherMicroprocessors and Microsystems
Academic DepartmentElectrical & Computer Engineering
DivisionEngineering
OrganizationLafayette College
Date IssuedApril 2005
Date Available2015-04-06T18:14:17Z
TypeArticle
LanguageEnglish
KeywordLee algorithm
hardware acceleration
VLSI routine
FPGA design
Bibliographic CitationNestor, J. A. (2005 Apr.) "L3: An FPGA-based multilayer maze routing accelerator." Microprocessors and Microsystems 29 (2-3): 87-97.
Standard IdentifierDOI 10.1016/j.micpro.2004.06.005
Handle 10385/1774
Permalinkhttp://hdl.handle.net/10385/1774
Rights Statement In Copyright In Copyright
Rights HoldersElsevier B. V.
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